The frequency synthesizer generates the high frequency signal at a controlled frequency, that is used in wireless communications and a wide variety of other applications. One widely used implementation of the synthesizer is the Phase-Lock Loop (PLL) system. Another type of synthesizer implements a frequency loop using counters pair/computer system, uses a pair of counters to concurrently count a reference signal and the oscillator (VCO) signal, to compute the frequency deviation and correct it in a closed loop.
Of paramount importance in wireless is efficient use of the frequency spectrum. It is difficult to accommodate the growing number of users of wireless, while the frequency spectrum remains fixed and limited. An effective answer is to better utilize the available spectrum, by transmitting more information (at higher bits/second rates) in the available spectrum (per each Hertz of bandwidth).
Frequency synthesizers are an important part of communication systems.
They are used both for transmission and reception, and influence the achievable rate of communication (bits/second). The lower the phase noise of the synthesizer, the lower is the Bit Error Rate (BER) of the communication channel.
The occurrence of errors requires the retransmission of messages and more overhead, resulting in a low overall communication speed, even if the initial bit rate was high. Thus, the phase noise limits the actual, effective communication speed. Therefore, low phase noise is required of a synthesizer for wireless communications.
The BER can be decreased by increasing the signal to noise ratio, that is by transmitting at a higher power. This has other disadvantages, like shorter battery lifetime and possible damage to users from radio frequency radiation. Moreover, the cost for the transmitter is higher. Accordingly, for a given transmission rate and BER, by lowering the phase noise of the synthesizer it is possible to use a lower transmitted power, thus the battery lasts longer and the possible damage from radiation is diminished.
PLL devices have a finite, distinctive phase noise which influences the wireless system performance. Frequency loop devices have higher phase noise, because of the quantization error and other effects.
Frequency settling time is another important parameter in frequency synthesizers. Spread spectrum by frequency hopping is a proven method for effective spectrum utilization. The method requires that the synthesizer change the output frequency at predefined times. It takes time for the synthesizer to switch to a new frequency, with the time lost in the process limiting the performance of the communication channel. Counter pair/computer devices have fast settling times, but their use in communication systems is limited because of phase noise, uncontrolled phase errors and other limitations.
PLL devices have a long settling time. These devices are usually described as linear, closed loop systems. But the linear model holds only for the PLL in locked state.
Prior to lock-on (that is, during the transition to a new frequency) the device is nonlinear, with a complex process including "beats" or the phase approaching to and departing from the lock-on value, until lock is achieved. The complex process presents a difficult to predict settling time.
Long-term frequency precision is another important requirement of frequency synthesizers. PLL devices have a definite advantage, since the oscillator phase is locked to the reference, and thus the output frequency is a precise multiple or submultiple of that reference. The problem is the instantaneous frequency, which may exhibit large excursions, as detailed later.
Phase-lock loops have a precise output frequency without error, whereas frequency loops usually have a frequency error because of the truncation error and limitations in the computer capability and speed/performance overall limits.
My previous disclosure, as detailed in Israeli Patent No. 096351 and U.S. Pat. No. 5,182,528, describes a digital frequency synthesizer using a smart, computer- controlled closed loop to generate a precisely controlled frequency. The closed loop comprises the oscillator, the digital frequency measurement means, and a computer which is connected back to the oscillator. This is a frequency loop. There is no phase lock between the reference and the output signal. This is not a PLL.
This prior art synthesizer has a fast frequency switching, but requires a complex computation to find the frequency ratio, since the accumulated count may achieve large values. The ratio computation may take time to perform. Moreover, there are no provisions to achieve low phase noise, an important consideration in communication systems. There are no provisions to achieve phase coherency between the reference signal and the oscillator signal, another desired property in precise signal generators.
Phase Lock Loops (PLL) used at present achieve a phase lock between a reference and the output signal. However, in these PLLs there is a difficult trade-off between frequency switching speed, the reference frequency, the output frequency increment and the phase noise.
For example, to achieve fine frequency increments a low reference frequency is required. This, however, results in higher phase noise because of the additional noise introduced during frequency multiplication. The lower the reference frequency, the slower is the frequency switching because of the low pass filter required. At present, a widely used solution is the fractional counter PLL which allows for both higher frequency reference and fine output increments. This solution however introduces phase noise and the frequency switching is still slow.
Taki, U.S. Pat. No. 5,459,435, discloses a frequency synchronous circuit for obtaining original clock signal by removing noise components. This is basically a frequency control closed loop, with two counters counting cycles of a reference signal and a VCO output, respectively. The counters are concurrently activated for a time period T each time, with the reading in the counters being indicative of the frequency error. The difference between the counter readings indicates the frequency deviation.
This structure includes a storage/average unit that is applied to the reference readings. The purpose of the system, apparently, is to address the problem of a noisy reference signal. By averaging the readings of the reference counter, the noise in the reference is decreased.
Thus, Taki is not a phase-locked system but a frequency loop system.
Frequency loop systems have a nonzero frequency error, this resulting in lower performance systems. The only operation on the bus is averaging. There is no scaling/normalization of one bus (either the reference or the VCO bus) so that the two digital buses represent phase in the same units to allow direct subtraction between these buses.
Ho, U.S. Pat. No. 5,363,419, discloses a dual phase-locked loop having forced mid range fine control zero at handover. The system includes a coarse frequency control loop and a fine phase-lock loop. There is a specific method of transferring control from the coarse loop to the fine loop. The coarse loop is a frequency control type having a frequency error, and thus does not provide the high performance as disclosed in the present invention. The fine loop is has a regular PLL structure as known in the art, using just one bit of the reference that is compared with only one bit of the VCO counter.
There is no scaling/normalization of one bus (either the reference or the VCO bus) so that the two digital buses represent phase in the same units to allow direct comparison between these buses.
Contemporary wireless systems usually use a phase-locked synthesizer for better performance. Of the above cited references, Zuta and Taki are frequency control loops that do not achieve phase lock. Ho uses a phase lock system, however the PLL itself does not include means for achieving higher performance, except the coarse loop for achieving faster lock-on. A fast lock-on is achieved for a high reference frequency (25 MHz in the cited example), this having the disadvantage of coarse frequency resolution. That is, the output frequency can only be set on 25 MHz increments, for example 900 MHz, 925 MHz, 950 MHz, 975 MHz etc.
Some of the most important characteristics of a frequency synthesizer include the frequency precision, low phase noise, fast frequency settling time and good frequency resolution. Good frequency precision is achieved with phase-lock loops, that feature a zero frequency error. This performance is superior to that achievable with frequency loops, that usually have a finite nonzero frequency error. Low phase noise usually requires a high reference frequency; this, however, prevents good frequency resolution (fine frequency steps). Fine frequency steps result in higher phase noise because of the frequency multiplication.
None of the above-mentioned references addresses the problem of concurrently improving all the above mentioned synthesizer characteristics in a phase-lock system: the phase noise, frequency settling time and the frequency resolution.
A description of a frequency synthesizer using digital bus correction/normalization was published by the present inventor in the June 1998 issue of the "Microwave Journal" magazine, pp. 94-108, titled "A New PLL with Fast Settling Time and Low Phase Noise".
It is an objective of the present invention to provide for a digital frequency synthesizer with means for overcoming the abovedetailed disadvantages.